High-Speed PCB Design Service
Once edge rates get fast enough, the board stops being wiring and starts being a transmission-line network. We design for that from the stackup up.
When a design becomes a high-speed design
It is edge rate, not clock frequency, that decides. A 10 MHz clock with a 500 ps rise time has meaningful energy well past 700 MHz, and a trace only a few centimetres long can already behave as a transmission line. If your design has any of the following, it needs high-speed treatment.
- USB 2.0 High-Speed, USB 3.x, or Ethernet at 100 Mbps and above
- DDR2/DDR3/DDR4 memory interfaces
- LVDS or MIPI display and camera links
- Any RF front end — sub-GHz, 2.4 GHz, GNSS, or cellular
- Switching regulators sharing a board with sensitive analogue measurement
- A product that must pass CE or FCC radiated-emissions testing
How we approach high-speed layout
Stackup first
The stackup is chosen before any routing happens. Every high-speed layer gets an adjacent solid reference plane, and dielectric thicknesses are set to hit the impedance targets at a trace width the fabricator can hold reliably.
Return-path continuity
We route so return current always has an uninterrupted path directly beneath the signal. Layer transitions on critical nets get stitching vias placed with the signal via, not added afterwards.
Impedance control
Single-ended 50Ω, differential 90Ω for USB, 100Ω for Ethernet and LVDS — calculated against the real stack and specified to the fabricator in the fab notes.
Power integrity
Decoupling is designed as a network across the frequency range rather than a scatter of 100 nF parts, with plane capacitance and placement working together.
EMC pre-compliance
Guard traces, edge-plane stitching, careful connector and cable-shield grounding, and containment of switching loops — the things that decide whether your first EMC test is a formality or a redesign.
RF and antenna integration
For designs with an integrated antenna — BLE, LoRa, Wi-Fi, or GNSS — we follow the module or chip vendor's reference layout closely, respect the required keep-out volumes, and design the matching network with test points so the antenna can actually be tuned on real hardware rather than hoped into working.
- 50Ω coplanar waveguide or microstrip feed lines with continuous ground stitching
- Pi-network matching footprints placed for straightforward tuning
- Ground-plane keep-outs sized per the antenna manufacturer's specification
- Component and connector placement that keeps RF away from switching noise sources
Common questions
Do you run signal integrity simulation?
For most designs, disciplined stackup and routing practice is what determines the outcome, and we prioritise that. Where a design genuinely warrants it — DDR fly-by topologies, long backplane runs — we scope simulation explicitly as part of the quote rather than assuming it.
Can you help a board that failed EMC testing?
Yes. We review the test report against the layout, identify the likely coupling or radiation mechanism, and propose a revision. In many cases the fix is a stackup or return-path change rather than a full redesign.
Do you design DDR memory interfaces?
Yes, including fly-by topology, length matching within the tolerances the memory controller requires, and reference-plane discipline across the whole byte lane. These designs are quoted individually after a review of the controller's layout guidelines.
Send us your design.
Schematic, block diagram, or a description of what you need built — you get a fixed-price quote with defined deliverables, usually within one business day.
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Last reviewed 2026-08-03 by Niloy Mondal, IPC CID+ certified PCB designer.