Guide

PCB Stackup Design: Choosing 2, 4, 6 and 8 Layers

The stackup is the most consequential decision in a layout and the one most often made by default. Get it right and routing becomes straightforward; get it wrong and no amount of careful routing recovers the design.

The one rule that matters most

Every signal layer should be directly adjacent to a solid, unbroken reference plane. Current returns along the path of least impedance, which at high frequency means directly beneath the trace. If there is no continuous plane there, the return current detours — and that detour is a loop, and that loop radiates and picks up noise.

Almost every other stackup guideline is a consequence of this one. When you evaluate a proposed stackup, ask of every signal layer: what plane is it referenced to, and is that plane continuous under the routing?

Standard stackups by layer count

Layers	Arrangement	Assessment
2	Signal / Signal	No true reference plane. Acceptable for low-speed only. Pour ground on the bottom and keep it as continuous as you can.
4 (recommended)	Signal / GND / PWR / Signal	The practical default. Both signal layers reference a plane. Thin the outer dielectric to improve coupling.
4 (avoid)	Signal / PWR / GND / Signal	Inferior. Top-layer signals reference a fragmented power plane.
6	Sig / GND / Sig / Sig / GND / Sig	Good for dense routing. Inner signal pair should route orthogonally.
6 (high-speed)	Sig / GND / Sig / PWR / GND / Sig	Better isolation and tight plane pairing for decoupling.
8	Sig / GND / Sig / PWR / GND / Sig / GND / Sig	Every signal layer referenced. The default for serious high-speed work.

Dielectric thickness and impedance

Trace impedance is set by trace width, dielectric thickness to the reference plane, copper thickness, and the dielectric constant of the material. Of those, the dielectric thickness is the lever you control at stackup time — and it is what makes a target impedance achievable at a sensible trace width.

For 50Ω single-ended microstrip on standard FR-4, a common combination is roughly 0.1 mm dielectric with a 0.18 mm trace, or 0.2 mm dielectric with a 0.36 mm trace.
A thick outer dielectric forces impractically wide traces — a frequent cause of designs that cannot hit their impedance target and quietly ship out of spec.
Standard FR-4 has a dielectric constant near 4.2–4.5 at low frequency, falling with frequency. For designs above a few GHz, ask your fabricator for the frequency-dependent value rather than assuming.
Always request the fabricator's actual stackup and have them confirm the impedance calculation. Do not rely solely on your EDA tool's field solver against assumed material properties.

Practical guidance

Keep the stackup symmetric about the centre. Asymmetric copper distribution warps the board during reflow.
Place power and ground planes adjacent to each other where you can — the interplane capacitance is useful high-frequency decoupling that costs nothing.
Route adjacent signal layers orthogonally to reduce broadside crosstalk.
Moving from 2 to 4 layers typically adds a modest amount per board at prototype quantities. Weigh that against the engineering hours and the EMC risk of forcing a 2-layer design.
Fix the stackup before routing begins. Changing it afterwards invalidates every impedance-controlled trace on the board.

Common questions

Is a 4-layer board always better than 2-layer?

For anything with a microcontroller, a switching regulator, or an EMC requirement, yes — the solid ground plane is worth far more than the added board cost. A 2-layer board remains reasonable for simple low-speed sensors and breakout boards.

Should I split the ground plane for analogue and digital?

Usually not. Split planes are one of the most common causes of EMC failure because signals crossing the split lose their return path. A single continuous ground plane with careful component placement and partitioning is almost always the better approach.

Do I need to specify impedance to the fabricator?

If your design has USB, Ethernet, LVDS, DDR, or any RF, yes. Provide an impedance table in the fab notes naming the layer, trace width, target impedance, and tolerance. Without it the fabricator builds to nominal thickness and your impedance is whatever it happens to be.

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Every board that gets built well follows roughly the same path. This is that path, described the way it actually runs on commercial projects — including the review gates that stop expensive mistakes reaching fabrication.

PCB DFM Checklist: What to Verify Before Sending Gerbers

A clean DRC does not mean a manufacturable board. This is the review we run on every design before release, and on client designs brought to us for a standalone DFM check.

Last reviewed 2026-08-03 by Niloy Mondal, IPC CID+ certified PCB designer.