Guide

PCB DFM Checklist: What to Verify Before Sending Gerbers

A clean DRC does not mean a manufacturable board. This is the review we run on every design before release, and on client designs brought to us for a standalone DFM check.

Copper features

Trace width and spacing meet the fabricator's standard process, not their finest capability — fine-line processes cost more and yield worse.
No acid traps: acute angles between copper features that trap etchant and over-etch.
No isolated copper slivers left by pour clearances.
Copper-to-board-edge clearance is respected, typically 0.25 mm or more.
Thermal reliefs on plane connections are adequate for hand rework but not so starved they cause voltage drop.
Copper balance across the panel is reasonably even to avoid etch and lamination variation.

Drills and vias

Annular ring meets the minimum for your class — IPC-2221 Class 2 is the usual commercial target.
Aspect ratio (board thickness to drill diameter) is within the fabricator's plating capability, commonly 8:1 to 10:1.
Drill-to-copper clearance is respected on all layers.
Vias under BGAs are tented or filled as the assembly process requires, so solder does not wick away from the joint.
Non-plated holes are on a separate drill layer and clearly identified.
No via count inflation from unnecessary layer changes on high-speed nets.

Solder mask and paste

Mask slivers between fine-pitch pads meet the minimum web width, or mask is deliberately removed between them.
Mask expansion is consistent and appropriate for the pad type.
Paste aperture area ratio is above roughly 0.66 for reliable release, especially on QFN thermal pads.
Large thermal pads use a windowpane paste pattern rather than a single aperture, to control void formation and prevent part float.
Test points and press-fit areas are correctly masked or exposed as intended.

Assembly geometry

Courtyards do not overlap — the placement head needs physical access.
Adequate clearance around tall components and connectors.
Fiducials present: at least three global fiducials, plus local fiducials on fine-pitch and BGA parts.
Polarity and pin-1 markers on silkscreen and, ideally, in copper where silkscreen may be obscured.
Silkscreen does not overlap pads — it will be clipped, potentially removing the reference designator entirely.
Panelisation, V-score, or mouse-bite tabs defined if assembly requires an array.
Component rotations in the centroid file match the assembly drawing convention.

Documentation

Fab notes specify material, finished thickness, copper weight, surface finish, solder mask and silkscreen colour, and IPC class.
Impedance table included if the design has controlled-impedance nets.
Layer order and orientation unambiguously defined in a stackup drawing.
Board outline provided on a dedicated mechanical layer with dimensions and tolerances.
Assembly drawing shows polarity, orientation, and any do-not-populate components.
BOM lists manufacturer part numbers, not just descriptions, with DNP items clearly marked.
Revision number present on the board in copper or silkscreen — you will thank yourself when three revisions are on the bench together.

Final verification

Re-import your own Gerbers

Open the generated files in an independent viewer. What the factory sees is the Gerber output, not your EDA database, and export settings do occasionally go wrong.

Compare netlist to schematic

Run an IPC-356 netlist comparison against the schematic to catch any net that changed during layout edits.

3D fit check

Export the STEP model and check it against the enclosure and any mating connectors before committing to fabrication.

Confirm against the capability sheet

Check the design against your chosen fabricator's current published capabilities. These change, and a design that was standard-process last year may not be this year.

Common questions

Is a passing DRC enough to send a board to fabrication?

No. A DRC checks the rules you configured, which are usually electrical and geometric defaults. It will not tell you that a mask sliver will fall off, that a paste aperture will not release, or that your annular ring is legal but marginal for your fabricator's registration accuracy.

What is the single most common DFM problem?

Footprint errors — wrong pad geometry, wrong pitch, or a mirrored pinout. They pass every automated check because the tool has no way to know the footprint disagrees with the physical part. Verify against the manufacturer's package drawing.

Can you run this review on a design I had done elsewhere?

Yes. A standalone DFM review is a common short engagement. You receive a written report with findings classified by severity, and we can implement the corrections if you want.

Send us your design.

Schematic, block diagram, or a description of what you need built — you get a fixed-price quote with defined deliverables, usually within one business day.

Request a quote

Every board that gets built well follows roughly the same path. This is that path, described the way it actually runs on commercial projects — including the review gates that stop expensive mistakes reaching fabrication.

PCB Stackup Design: Choosing 2, 4, 6 and 8 Layers

The stackup is the most consequential decision in a layout and the one most often made by default. Get it right and routing becomes straightforward; get it wrong and no amount of careful routing recovers the design.

Last reviewed 2026-08-03 by Niloy Mondal, IPC CID+ certified PCB designer.